#include <p18f2550.h>
// PIC18F2550 Configuration Bit Settings

// 'C' source line config statements

#include <xc.h>

// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.

// CONFIG1L
#pragma config PLLDIV = 1       // PLL Prescaler Selection bits (No prescale (4 MHz oscillator input drives PLL directly))
#pragma config CPUDIV = OSC1_PLL2// System Clock Postscaler Selection bits ([Primary Oscillator Src: /1][96 MHz PLL Src: /2])
#pragma config USBDIV = 1       // USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1) (USB clock source comes directly from the primary oscillator block with no postscale)

// CONFIG1H
#pragma config FOSC = XT_XT     // Oscillator Selection bits (XT oscillator (XT))
#pragma config FCMEN = OFF      // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
#pragma config IESO = OFF       // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)

// CONFIG2L
#pragma config PWRT = OFF       // Power-up Timer Enable bit (PWRT disabled)
#pragma config BOR = ON         // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
#pragma config BORV = 3         // Brown-out Reset Voltage bits (Minimum setting)
#pragma config VREGEN = OFF     // USB Voltage Regulator Enable bit (USB voltage regulator disabled)

// CONFIG2H
#pragma config WDT = OFF        // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
#pragma config WDTPS = 32768    // Watchdog Timer Postscale Select bits (1:32768)

// CONFIG3H
#pragma config CCP2MX = ON      // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
#pragma config PBADEN = ON      // PORTB A/D Enable bit (PORTB<4:0> pins are configured as analog input channels on Reset)
#pragma config LPT1OSC = OFF    // Low-Power Timer 1 Oscillator Enable bit (Timer1 configured for higher power operation)
#pragma config MCLRE = ON       // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)

// CONFIG4L
#pragma config STVREN = ON      // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
#pragma config LVP = OFF        // Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
#pragma config XINST = OFF      // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))

// CONFIG5L
#pragma config CP0 = OFF        // Code Protection bit (Block 0 (000800-001FFFh) is not code-protected)
#pragma config CP1 = OFF        // Code Protection bit (Block 1 (002000-003FFFh) is not code-protected)
#pragma config CP2 = OFF        // Code Protection bit (Block 2 (004000-005FFFh) is not code-protected)
#pragma config CP3 = OFF        // Code Protection bit (Block 3 (006000-007FFFh) is not code-protected)

// CONFIG5H
#pragma config CPB = OFF        // Boot Block Code Protection bit (Boot block (000000-0007FFh) is not code-protected)
#pragma config CPD = OFF        // Data EEPROM Code Protection bit (Data EEPROM is not code-protected)

// CONFIG6L
#pragma config WRT0 = OFF       // Write Protection bit (Block 0 (000800-001FFFh) is not write-protected)
#pragma config WRT1 = OFF       // Write Protection bit (Block 1 (002000-003FFFh) is not write-protected)
#pragma config WRT2 = OFF       // Write Protection bit (Block 2 (004000-005FFFh) is not write-protected)
#pragma config WRT3 = OFF       // Write Protection bit (Block 3 (006000-007FFFh) is not write-protected)

// CONFIG6H
#pragma config WRTC = OFF       // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) are not write-protected)
#pragma config WRTB = OFF       // Boot Block Write Protection bit (Boot block (000000-0007FFh) is not write-protected)
#pragma config WRTD = OFF       // Data EEPROM Write Protection bit (Data EEPROM is not write-protected)

// CONFIG7L
#pragma config EBTR0 = OFF      // Table Read Protection bit (Block 0 (000800-001FFFh) is not protected from table reads executed in other blocks)
#pragma config EBTR1 = OFF      // Table Read Protection bit (Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks)
#pragma config EBTR2 = OFF      // Table Read Protection bit (Block 2 (004000-005FFFh) is not protected from table reads executed in other blocks)
#pragma config EBTR3 = OFF      // Table Read Protection bit (Block 3 (006000-007FFFh) is not protected from table reads executed in other blocks)

// CONFIG7H
#pragma config EBTRB = OFF      // Boot Block Table Read Protection bit (Boot block (000000-0007FFh) is not protected from table reads executed in other blocks)
#include <plib.h>
void main() {
    // Para cambiar de 1 a 2 cifra se usa el '=', para pasar de la 2 a la 3 se usa '+' y asi sucesivamente, y luego al final se usa el '-' para mostrar todo el numero ingresado.
    ADCON1=15;
    TRISA=0;
    TRISB=240;
    TRISC=0;
    PORTC=63;
    Delay10KTCYx(1000);
    int C=0,Dm,Um,Ce,D,U=0;
    for(;;){

        if(C==0){PORTC=1;
        PORTB=1;
        if(PORTB==17){PORTA=1;}
        else if(PORTB==33){PORTA=2;}
        else if(PORTB==65){PORTA=3;}
        PORTB=2;
        if(PORTB==18){PORTA=4;}
        else if(PORTB==34){PORTA=5;}
        else if(PORTB==66){PORTA=6;}
        PORTB=4;
        if(PORTB==20){PORTA=7;}
        else if(PORTB==36){PORTA=8;}
        else if(PORTB==68){PORTA=9;}
        PORTB=8;
        if(PORTB==40){PORTA=0;}
        else if(PORTB==72){C++;}
        else if(PORTB==136){}
        PORTB=0;
        Delay10KTCYx(1);
        Dm=PORTA;
        }
        /***************************************/
        else if(C==1){PORTC=2;
        PORTB=1;
        if(PORTB==17){PORTA=1;}
        else if(PORTB==33){PORTA=2;}
        else if(PORTB==65){PORTA=3;}
        PORTB=2;
        if(PORTB==18){PORTA=4;}
        else if(PORTB==34){PORTA=5;}
        else if(PORTB==66){PORTA=6;}
        PORTB=4;
        if(PORTB==20){PORTA=7;}
        else if(PORTB==36){PORTA=8;}
        else if(PORTB==68){PORTA=9;}
        PORTB=8;
        if(PORTB==40){PORTA=0;}
        else if(PORTB==72){PORTA=0;}
        else if(PORTB==136){C++;}
        PORTB=0;
        Delay10KTCYx(1);
        Um=PORTA;
        }
        /**************************************************/
        else if(C==2){PORTC=4;
        PORTB=1;
        if(PORTB==17){PORTA=1;}
        else if(PORTB==33){PORTA=2;}
        else if(PORTB==65){PORTA=3;}
        PORTB=2;
        if(PORTB==18){PORTA=4;}
        else if(PORTB==34){PORTA=5;}
        else if(PORTB==66){PORTA=6;}
        PORTB=4;
        if(PORTB==20){PORTA=7;}
        else if(PORTB==36){PORTA=8;}
        else if(PORTB==68){PORTA=9;}
        PORTB=8;
        if(PORTB==24){}
        else if(PORTB==40){}
        else if(PORTB==72){C++;}
        else if(PORTB==136){PORTA=0;}
        PORTB=0;
        Delay10KTCYx(1);
        Ce=PORTA;
        }
        /*************************************/
        else if(C==3){PORTC=16;
        PORTB=1;
        if(PORTB==17){PORTA=1;}
        else if(PORTB==33){PORTA=2;}
        else if(PORTB==65){PORTA=3;}
        PORTB=2;
        if(PORTB==18){PORTA=4;}
        else if(PORTB==34){PORTA=5;}
        else if(PORTB==66){PORTA=6;}
        PORTB=4;
        if(PORTB==20){PORTA=7;}
        else if(PORTB==36){PORTA=8;}
        else if(PORTB==68){PORTA=9;}
        PORTB=8;
        if(PORTB==24){}
        else if(PORTB==40){}
        else if(PORTB==72){PORTA=0;}
        else if(PORTB==136){C++;}
        PORTB=0;
        Delay10KTCYx(1);
        D=PORTA;
        }
        /****************************************/
      else if(C==4){PORTC=32;
        PORTB=1;
        if(PORTB==17){PORTA=1;}
        else if(PORTB==33){PORTA=2;}
        else if(PORTB==65){PORTA=3;}
        PORTB=2;
        if(PORTB==18){PORTA=4;}
        else if(PORTB==34){PORTA=5;}
        else if(PORTB==66){PORTA=6;}
        PORTB=4;
        if(PORTB==20){PORTA=7;}
        else if(PORTB==36){PORTA=8;}
        else if(PORTB==68){PORTA=9;}
        else if(PORTB==132){C++;}
        PORTB=8;
        if(PORTB==24){}
        else if(PORTB==40){}
        else if(PORTB==72){}
        else if(PORTB==136){PORTA=0;}
        PORTB=0;
        Delay10KTCYx(1);
        U=PORTA;
        }


        /*********************
         ****************************************** */


      else if(C==5){
          PORTA=Dm;
          PORTC=1;
          Delay10KTCYx(5);
          PORTA=Um;
          PORTC=2;
          Delay10KTCYx(5);
          PORTA=Ce;
          PORTC=4;
          Delay10KTCYx(5);
          PORTA=D;
          PORTC=16;
          Delay10KTCYx(5);
          PORTA=U;
          PORTC=32;
          Delay10KTCYx(5);

      }
    }
    
}


